Multiple-processor systems generally are configured so that many regions of a memory are shared by more than one processor. Typically, each processor utilizes one or more local caches to maintain copies of data accessed from shared memory. Due to the shared nature of the memory and its stored data, multiple-processor systems typically utilize a cache coherency protocol in an attempt to maintain all of the caches in a state of coherence so that a change to the local copy of a shared memory location can propagate to other processors as necessary. One conventional cache coherency technique includes the use of a coherency directory at each processing node that stores the cache state for each local memory location shared with other processing nodes. In response to processing a memory transaction for a memory location, each processor of the processing node reports compliance with the coherency requirements of the memory transaction. The coherency directory updates its coherency state information based on assumptions made from the reported compliance and routes subsequent memory transactions based on the cache state information for the memory locations associated with the memory transactions. However, these coherency compliance reports often are misleading or incomplete in conventional directory-based coherency systems as they fail to establish with any certainty the cumulative coherency state of the accessed memory location for the processor. Rather, these coherency compliance responses typically only acknowledge compliance with the coherency requirements associated with the memory transaction and may not represent the true coherency state in the cache hierarchy of the processor. Accordingly, it will be appreciated that a technique for enforcing the reporting of the true cache coherency state in a multiple-processor system would be advantageous.
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